On-the- y Programmable Hardware for Networks

Ilija Hadzic and Jonathan M. Smith Distributed Systems Laboratory, University of Pennsylvania [email protected], [email protected] Abstract Ongoing research in adaptive protocols and active networks has presumed that exibility is o ered exclusively through software systems, and the performance implications have generated considerable skepticism. The Programmable Protocol Processing Pipeline (P4) exploits the dynamic recon gurability of RAM based Field Programmable Gate Arrays (FPGAs) to provide both hardware performance and dynamic functionality to network components. We use forward error correction (FEC) as an example of a protocol processing function. Our measurements show that the P4 is able to process the data stream at OC-3 (155 Mbps) link rate, and consequently improve TCP performance in noisy environments.